The present application relates to semiconductor devices, and more particularly to trench device structure and fabrication.
Trench MOSFET devices being manufactured today have their source regions formed by implanting the required dopant species.
Note that the points discussed below may reflect the hindsight gained from the disclosed inventions, and are not necessarily admitted to be prior art.
With reference to FIG. 1, a vertical DMOS transistor is shown. This Figure is from U.S. Pat. No. 5,663,079, which is incorporated by reference in the present application. Gate regions 12 are formed within a gate dielectric layer 17. P− body regions 18 are diffused into the epi layer (or substrate) 10. A second layer of polycrystalline silicon 11 is deposited. The second polysilicon layer 11 is N-type doped using phosphorus, arsenic or antimony.
A layer of silicon dioxide 19 is deposited on the polysilicon 11 and the exposed parts of the silicon substrate 10, The n-type dopant in the second polysilicon layer 11 forms the diffused n-type source regions 14. P-type dopant is introduced and diffused to the desired depth forming p+ region 16 which is shown as being shallower than p− body region 18, but may be the same depth, or deeper, than p− body region 18. Separate contact regions 13, 15 are opened through insulating layer 19 to the polysilicon layer to electrically contact the source region 14. This structure allows the contact to the source polysilicon to be made a distance from the diffused source region in the silicon.